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MC74HCT273A Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS
The MC74HCT273A may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. The HCT273A is identical in pinout to the LS273. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low.
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20 PDIP-20 N SUFFIX CASE 738
1
20
MC74HCT273AN AWLYYWW 1 20
* * * * * * * w
Output Drive Capability: 10 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 284 FETs or 71 Equivalent Gates
These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
20
1
SOIC WIDE-20 DW SUFFIX CASE 751D 1 A WL YY WW
HCT273A AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week
PIN ASSIGNMENT
RESET Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK
ORDERING INFORMATION
Device MC74HCT273AN MC74HCT273ADW Package PDIP-20 SOIC-WIDE Shipping 1440 / Box 38 / Rail 1000 / Reel
MC74HCT273ADWR2 SOIC-WIDE
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 10
1
Publication Order Number: MC74HCT273A/D
MC74HCT273A
LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK 3 4 7 8 13 14 17 18 11 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
RESET
1
PIN 20 = VCC PIN 10 = GND
FUNCTION TABLE
Inputs Reset L H H H H Clock X D X H L X X Output Q L H L No Change No Change
L
X = Don't Care Z = High Impedance
II I II I IIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I III II I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II
Symbol VCC Vin Iin Vout Iout PD Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW _C _C Tstg TL - 65 to + 150 260 Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or Plastic DIP)
MAXIMUM RATINGS*
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
III I I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I III I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIII IIIIIIIIIIIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII
VCC TA DC Supply Voltage (Referenced to GND) 4.5 0 5.5 V V Vin, Vout tr, tf DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC 500 - 55 0 + 125 _C ns
Symbol
Parameter
Min
Max
Unit
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MC74HCT273A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I II II II I I I I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I
Guaranteed Limit v 85_C 2.0 2.0 0.8 0.8 4.4 5.4 Symbol VIH VIL Parameter Test Conditions VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 - 55 to 25_C 2.0 2.0 0.8 0.8 4.4 5.4 v 125_C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 Unit V V V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL |Iout| v 4.0 mA Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL |Iout| v 4.0 mA Maximum Low-Level Input Voltage VOH Minimum High-Level Output Voltage 3.98 0.1 0.1 3.84 0.1 0.1 VOL Maximum Low-Level Output Voltage V 0.26 0.33 Iin Maximum Input Leakage Current Vin = VCC or GND 0.1 4.0 1.0 40 1.0 160 A A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 A ICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 A -55_C 2.9 25_C to 125_C 2.4 5.5 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit v 85_C 24 28 28 20 - 55 to 25_C 30 25 25 18 Symbol fmax Parameter Fig. 1, 4 1, 4 2, 4 1, 5 v 125_C 20 35 35 22 Unit Maximum Clock Frequency (50% Duty Cycle) Maximum Propagation Delay, Clock to Q MHz ns ns ns tPLH, tPHL tPHL Maximum Propagation Delay, Reset to Q tTLH, tTHL Maximum Output Transition Time, Any Output NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 30
2f + I CC
CPD
Power Dissipation Capacitance (Per Gate)*
pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D).
VCC . For load considerations, see Chapter 2 of the
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I III II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I III II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I III II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
TIMING REQUIREMENTS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tr, tf trec tsu tw tw th Maximum Input Rise and Fall Times Minimum Pulse Width, Set or Reset Minimum Pulse Width, Clock Minimum Recovery Time, Set or Reset Inactive to Clock Minimum Hold Time, Clock to Data Minimum Setup Time, Data to Clock Parameter
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MC74HCT273A
4 Fig. 1 2 1 2 3 3 - 55 to 25_C Min 5.0 3.0 12 12 10 Max 500 Guaranteed Limit Min 5.0 3.0 15 15 12 v 85_C Max 500 Min 5.0 3.0 18 18 15 v 125_C Max 500 Unit ns ns ns ns ns ns
MC74HCT273A
SWITCHING WAVEFORMS
tr CLOCK 2.7 V 1.3 V 0.3 V tw 1/fmax tPLH Q 90% 1.3 V 10% tTLH tTHL tPHL tf 3.0 V GND Q RESET 1.3 V tPHL 1.3 V trec CLOCK 1.3 V tw 3.0 V GND
3.0 V GND
Figure 1.
Figure 2.
TEST POINT
VALID DATA 1.3 V tsu CLOCK th 1.3 V
3.0 V GND 3.0 V GND
OUTPUT DEVICE UNDER TEST C L*
*Includes all probe and jig capacitance
Figure 3. EXPANDED LOGIC DIAGRAM
D0 3 C DR C DR C DR C DR C DR C DR C DR C DR Q 2
Figure 4. Test Circuit
Q0
D1
4
Q
5
Q1
D2
7
Q
6
Q2
DATA INPUTS
D3
8
Q
9
Q3
D4
13
Q
12
NONINVERTING OUTPUTS
Q4
D5
14
Q
15
Q5
D6
17
Q
16
Q6
D7 CLOCK RESET
18 11 1
Q
19
Q7
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MC74HCT273A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
11
-A-
20 1
B
10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
M
0.25 (0.010) TA
M
M
TB
M
SO-20 DW SUFFIX CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
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L
MC74HCT273A
Notes
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MC74HCT273A
Notes
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MC74HCT273A/D

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